The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 17, 2023
Filed:
Feb. 22, 2019
Intel Corporation, Santa Clara, CA (US);
Sansaptak Dasgupta, Hillsboro, OR (US);
Marko Radosavljevic, Portland, OR (US);
Han Wui Then, Portland, OR (US);
Paul B. Fischer, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Disclosed herein are IC structures, packages, and devices that include III-N transistors integrated on the same support structure as non-III-N transistors (e.g., Si-based transistors), using semiconductor layer transfer. In one aspect, a non-III-N transistor may be integrated with an III-N transistor by, first, depositing a semiconductor material layer, a portion of which will later serve as a channel material of the non-III-N transistor, on a support structure different from that on which the III-N semiconductor material for the III-N transistor is provided, and then performing layer transfer of said semiconductor material layer to the support structure with the III-N material, e.g., by oxide-to-oxide bonding, advantageously enabling implementation of both types of transistors on a single support structure. Such integration may reduce costs and improve performance by enabling integrated digital logic solutions for III-N transistors and by reducing losses incurred when power is routed off chip in a multi-chip package.