The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 10, 2023

Filed:

May. 28, 2021
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Jonathan Almeria Noquil, Plano, TX (US);

Makarand Ramkrishna Kulkarni, Dallas, TX (US);

Osvaldo Jorge Lopez, Annandale, NJ (US);

Yiqi Tang, Allen, TX (US);

Rajen Manicon Murugan, Dallas, TX (US);

Liang Wan, Chengdu, CN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49822 (2013.01); H01L 23/49844 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/16238 (2013.01);
Abstract

In some examples, a semiconductor package comprises a multi-layer package substrate. The multi-layer package substrate includes first and second metal layers, the first metal layer positioned above the second metal layer and coupled to the second metal layer by way of a via. The substrate also includes a dielectric covering at least part of the first and second metal layers and the via. The package includes a plated metal layer plated on at least part of the first metal layer and positioned above the dielectric, a combination of the first metal layer and the plated metal layer being thicker than the second metal layer. The package includes a semiconductor die having a device side, the device side vertically aligned with and coupled to the plated metal layer.


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