The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 03, 2023

Filed:

Jun. 14, 2022
Applicant:

Industrial Technology Research Institute, Hsinchu, TW;

Inventors:

Kuo-Shu Kao, Hsinchu, TW;

Tao-Chih Chang, Taoyuan, TW;

Wen-Chih Chen, Hsinchu County, TW;

Tai-Jyun Yu, Taoyuan, TW;

Po-Kai Chiu, Taoyuan, TW;

Yen-Ting Lin, Hsinchu, TW;

Wei-Kuo Han, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/367 (2006.01); H01L 23/31 (2006.01); H01L 23/495 (2006.01); H01L 23/373 (2006.01); H01L 23/433 (2006.01);
U.S. Cl.
CPC ...
H01L 23/367 (2013.01); H01L 23/3157 (2013.01); H01L 23/3731 (2013.01); H01L 23/4334 (2013.01); H01L 23/4951 (2013.01); H01L 23/49531 (2013.01); H01L 23/49575 (2013.01); H01L 23/49586 (2013.01); H01L 23/3121 (2013.01); H01L 2224/26175 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48137 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/181 (2013.01);
Abstract

A chip package including a heat-dissipating device, a first thermal interface material layer disposed on the heat-dissipating device, a patterned circuit layer disposed on the first thermal interface material layer, a chip disposed on the patterned circuit layer and electrically connected to the patterned circuit layer, and an insulating encapsulant covering the chip, the patterned circuit layer, and the first thermal interface material layer is provided. The first thermal interface material layer has a thickness between 100 μm and 300 μm. The first thermal interface material layer is located between the patterned circuit layer and the heat-dissipating device.


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