The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 26, 2023

Filed:

May. 13, 2021
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Rainer Yen-Chieh Huang, Changhua County, TW;

Hai-Ching Chen, Hsinchu, TW;

Yu-Ming Lin, Hsinchu, TW;

Chung-Te Lin, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 29/78 (2006.01); H01L 29/417 (2006.01); H10B 51/20 (2023.01); H10B 51/30 (2023.01);
U.S. Cl.
CPC ...
H01L 29/516 (2013.01); H01L 29/40111 (2019.08); H01L 29/41725 (2013.01); H01L 29/6656 (2013.01); H01L 29/6684 (2013.01); H01L 29/78391 (2014.09); H10B 51/20 (2023.02); H10B 51/30 (2023.02);
Abstract

The present disclosure relates to an integrated circuit (IC) chip including a memory cell with a carrier barrier layer for threshold voltage tuning. The memory cell may, for example, include a gate electrode, a ferroelectric structure, and a semiconductor structure. The semiconductor structure is vertically stacked with the gate electrode and the ferroelectric structure, and the ferroelectric structure is between the gate electrode and the semiconductor structure. A pair of source/drain electrodes is laterally separated and respectively on opposite sides of the gate electrode, and a carrier barrier layer separates the source/drain electrodes from the semiconductor structure.


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