The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 19, 2023

Filed:

May. 10, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Blandine Duriez, Brussels, BE;

Georgios Vellianitis, Heverlee, BE;

Gerben Doornbos, Kessel-Lo, BE;

Marcus Johannes Henricus Van Dal, Linden, BE;

Martin Christopher Holland, San Jose, CA (US);

Timothy Vasen, Tervuren, BE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/786 (2006.01); H01L 29/08 (2006.01); H01L 21/306 (2006.01); H01L 21/3105 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 29/417 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66772 (2013.01); H01L 21/30625 (2013.01); H01L 21/31053 (2013.01); H01L 21/823418 (2013.01); H01L 21/823814 (2013.01); H01L 29/0847 (2013.01); H01L 29/41783 (2013.01); H01L 29/6656 (2013.01); H01L 29/66545 (2013.01); H01L 29/78603 (2013.01);
Abstract

In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a channel region of a semiconductor layer, a source/drain epitaxial layer is formed on opposing sides of the dummy gate structure, a planarization operation is performed on the source/drain epitaxial layer, the planarized source/drain epitaxial layer is patterned, the dummy gate structure is removed to form a gate space, and a metal gate structure is formed in the gate space.


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