The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 19, 2023

Filed:

May. 09, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Chun Hsiung Tsai, Hsinchu County, TW;

Kuo-Feng Yu, Hsinchu County, TW;

Yu-Ming Lin, Hsinchu, TW;

Clement Hsingjen Wann, Carmel, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 29/66 (2006.01); H01L 29/08 (2006.01); H01L 21/265 (2006.01); H01L 21/3105 (2006.01); H01L 21/762 (2006.01); H01L 21/266 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66545 (2013.01); H01L 21/02164 (2013.01); H01L 21/02332 (2013.01); H01L 21/26513 (2013.01); H01L 29/0847 (2013.01); H01L 29/6659 (2013.01); H01L 29/66553 (2013.01); H01L 29/66795 (2013.01); H01L 21/266 (2013.01); H01L 21/31053 (2013.01); H01L 21/76224 (2013.01); H01L 29/665 (2013.01);
Abstract

A method of manufacturing a semiconductor device includes: providing a substrate comprising a surface; depositing a first dielectric layer and a second dielectric layer over the substrate; performing a first treatment by introducing a trap-repairing element on the first and second dielectric layers; forming a dummy gate electrode over the second dielectric layer; forming a gate spacer surrounding the dummy gate electrode; forming lightly-doped source/drain (LDD) regions in the substrate on two sides of the gate spacer; forming source/drain regions in the respective LDD regions; removing the dummy gate electrode to form a replacement gate; and forming an inter-layer dielectric (ILD) layer over the replacement gate and the source/drain regions.


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