The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 12, 2023

Filed:

Nov. 23, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Mrunal A Khaderbad, Hsinchu, TW;

Yasutoshi Okuno, Hsinchu, TW;

Sung-Li Wang, Zhubei, TW;

Pang-Yen Tsai, Jhubei, TW;

Shen-Nan Lee, Jhudong Township, TW;

Teng-Chun Tsai, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/485 (2006.01); H01L 21/768 (2006.01); H01L 29/66 (2006.01); H01L 21/311 (2006.01); H01L 21/02 (2006.01); H01L 21/285 (2006.01); H01L 29/417 (2006.01); H01L 29/78 (2006.01); H01L 21/8234 (2006.01); H01L 29/45 (2006.01); H01L 21/8238 (2006.01); H01L 23/532 (2006.01); H01L 23/528 (2006.01); H01L 29/08 (2006.01); H01L 29/41 (2006.01);
U.S. Cl.
CPC ...
H01L 23/485 (2013.01); H01L 21/02634 (2013.01); H01L 21/28562 (2013.01); H01L 21/31116 (2013.01); H01L 21/76814 (2013.01); H01L 21/76822 (2013.01); H01L 21/76826 (2013.01); H01L 21/76831 (2013.01); H01L 21/76846 (2013.01); H01L 21/76847 (2013.01); H01L 21/823431 (2013.01); H01L 21/823821 (2013.01); H01L 23/528 (2013.01); H01L 23/532 (2013.01); H01L 29/0847 (2013.01); H01L 29/41 (2013.01); H01L 29/417 (2013.01); H01L 29/41791 (2013.01); H01L 29/456 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/7848 (2013.01);
Abstract

A semiconductor device and a method of forming the same are provided. A method includes forming a gate over a semiconductor structure. An epitaxial source/drain region is formed adjacent the gate. A dielectric layer is formed over the epitaxial source/drain region. An opening extending through the dielectric layer and exposing the epitaxial source/drain region is formed. A conductive material is non-conformally deposited in the opening. The conductive material fills the opening in a bottom-up manner.


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