The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 05, 2023

Filed:

Oct. 13, 2021
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Lakshminarayan Viswanathan, Chandler, AZ (US);

Jaynal A. Molla, Gilbert, AZ (US);

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/786 (2006.01); H01L 23/00 (2006.01); H01L 21/768 (2006.01); H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
H01L 24/83 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 24/05 (2013.01); H01L 24/29 (2013.01); H01L 24/32 (2013.01); H01L 2224/05572 (2013.01); H01L 2224/29022 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/83026 (2013.01); H01L 2224/8384 (2013.01); H01L 2924/1033 (2013.01); H01L 2924/10272 (2013.01); H01L 2924/13091 (2013.01);
Abstract

Die-substrate assemblies having sinter-bonded backside via structures, and methods for fabricating such die-substrate assemblies, are disclosed. In embodiments, the method includes obtaining an integrated circuit (IC) die having a backside over which a backmetal layer is formed and into which a plated backside via extends. The IC die is attached to an electrically-conductive substrate by: (i) applying sinter precursor material over the backmetal layer and into the plated backside via; (ii) positioning a frontside of the electrically-conductive substrate adjacent the plated backmetal layer and in contact with the sinter precursor material; and (iii) sintering the sinter precursor material to yield a sintered bond layer attaching and electrically coupling the IC die to the frontside of the electrically-conductive substrate through the backmetal layer and through the plated backside via. The sintered bond layer contacts and is metallurgically bonded to the backside via lining.


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