The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 05, 2023

Filed:

Nov. 03, 2022
Applicant:

Xintec Inc., Taoyuan, TW;

Inventors:

Chia-Ming Cheng, New Taipei, TW;

Shu-Ming Chang, New Taipei, TW;

Assignee:

XINTEC INC., Taoyuan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 23/552 (2006.01); H01L 23/66 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 23/552 (2013.01); H01L 21/565 (2013.01); H01L 23/3135 (2013.01); H01L 23/5226 (2013.01); H01L 23/5286 (2013.01); H01L 23/66 (2013.01); H01L 2223/6605 (2013.01); H01L 2223/6677 (2013.01);
Abstract

A chip package includes a first substrate, a second substrate, a first conductive layer, and a metal layer. The first substrate has a bottom surface and an inclined sidewall adjoining the bottom surface, and an obtuse angle is between the bottom surface and the inclined sidewall. The second substrate is over the first substrate and has a portion that laterally extends beyond the inclined sidewall of the first substrate. The first conductive layer is between the first substrate and the second substrate. The metal layer is on said portion of the second substrate, on the bottom surface and the inclined sidewall of the first substrate, and electrically connected to an end of the first conductive layer.


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