The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 29, 2023

Filed:

Nov. 13, 2019
Applicant:

Entegris, Inc., Billerica, MA (US);

Inventors:

Yan Liu, Lexington, MA (US);

Jakub Rybczynski, Arlington, MA (US);

Steven Donnell, Burlington, MA (US);

Chun Wang Chan, Cambridge, MA (US);

Assignee:

ENTEGRIS, INC., Billerica, MA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02N 13/00 (2006.01); H01L 21/683 (2006.01); B23Q 3/152 (2006.01);
U.S. Cl.
CPC ...
H02N 13/00 (2013.01); B23Q 3/152 (2013.01); H01L 21/6831 (2013.01); H01L 21/6833 (2013.01);
Abstract

An electrostatic chuck solves the problem of wafer sticking by providing conductive paths on raised embossments that are bridged together and are connected to ground that support the wafer substrate above the surface of the electrostatic chuck. Further, laterally spaced electrode patterns and electrode elements which are spaced laterally and longitudinally away from the raised embossments reduce or eliminate electrical coupling during wafer clamping between conductively coated embossments and the electrode elements, thereby creating a low resistance path for charges remaining on the wafer after declamping to promptly travel to ground. The conductive bridge and electrode pattern configuration also substantially reduces or eliminates any charge build up on the conductive bridge(s) during clamping in order that charge build up in 'islands' (worn portions of the insulator layer of the main field area) do not affect the charge dissipation from the wafer substrate through the conductive bridges to ground.


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