The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 29, 2023

Filed:

May. 17, 2021
Applicant:

Mediatek Inc., Hsin-Chu, TW;

Inventors:

Nai-Wei Liu, Hsin-Chu, TW;

Yen-Yao Chi, Hsin-Chu, TW;

Tzu-Hung Lin, Hsin-Chu, TW;

Wen-Sung Hsu, Hsin-Chu, TW;

Assignee:

MediaTek Inc., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01Q 1/22 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01); H01L 23/66 (2006.01); H01L 23/00 (2006.01); H01Q 1/38 (2006.01); H01Q 9/16 (2006.01);
U.S. Cl.
CPC ...
H01Q 1/2283 (2013.01); H01L 23/3128 (2013.01); H01L 23/3135 (2013.01); H01L 23/5384 (2013.01); H01L 23/5386 (2013.01); H01L 23/5389 (2013.01); H01L 23/66 (2013.01); H01L 24/20 (2013.01); H01Q 1/38 (2013.01); H01Q 9/16 (2013.01); H01L 2223/6677 (2013.01); H01L 2224/211 (2013.01); H01L 2224/221 (2013.01);
Abstract

A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor die surrounded by a first molding compound layer. A redistribution layer (RDL) structure is formed on a non-active surface of the semiconductor die and the first molding compound layer. A second molding compound layer is formed on the RDL structure. An insulating capping layer covers the second molding compound layer. An antenna is electrically coupled to the semiconductor die and includes a first antenna element formed in the RDL structure and a second antenna element formed between the second molding compound layer and the insulating capping layer.


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