The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 29, 2023

Filed:

Feb. 26, 2021
Applicants:

Stmicroelectronics Ltd, Kowloon, HK;

Stmicroelectronics Pte Ltd, Singapore, SG;

Inventors:

David Gani, Choa Chu Kang, SG;

Yiying Kuo, Taoyuan, TW;

Assignees:

STMICROELECTRONICS LTD, Kowloon, HK;

STMICROELECTRONICS PTE LTD, Singapore, SG;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/0203 (2014.01); H01L 31/18 (2006.01); H01L 31/0392 (2006.01); H01L 31/02 (2006.01); H01L 21/78 (2006.01);
U.S. Cl.
CPC ...
H01L 31/0203 (2013.01); H01L 21/78 (2013.01); H01L 31/02002 (2013.01); H01L 31/02005 (2013.01); H01L 31/0392 (2013.01); H01L 31/1876 (2013.01); H01L 31/1896 (2013.01);
Abstract

The present disclosure is directed to a package, such as a wafer level chip scale package (WLCSP), with a die coupled to a central portion of a transparent substrate. The transparent substrate includes a central portion having and a peripheral portion surrounding the central portion. The package includes a conductive layer coupled to a contact of the die within the package that extends from the transparent substrate to an active surface of the package. The active surface is utilized to mount the package within an electronic device or to a printed circuit board (PCB) accordingly. The package includes a first insulating layer separating the die from the conductive layer, and a second insulating layer on the conductive layer.


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