The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 15, 2023

Filed:

Mar. 14, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Stephen Harvey Hall, Forest Grove, OR (US);

Khang Choong Yong, Puchong, MY;

Ying Ern Ho, Bayan Lepas, MY;

Yun Rou Lim, Bayan Lepas, MY;

Wil Choon Song, Bayan Lepas, MY;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/02 (2006.01); G05B 19/4097 (2006.01); H05K 3/02 (2006.01); H05K 1/18 (2006.01);
U.S. Cl.
CPC ...
H05K 1/0225 (2013.01); G05B 19/4097 (2013.01); H05K 3/027 (2013.01); G05B 2219/45026 (2013.01); G05B 2219/45034 (2013.01); H05K 1/18 (2013.01); H05K 2201/093 (2013.01); H05K 2201/098 (2013.01); H05K 2201/09027 (2013.01); H05K 2201/10098 (2013.01);
Abstract

Apparatuses and methods are provided for mitigating radio frequency interference and electromagnetic compatibility issues caused by the resonance of metal planes of a circuit board. A method for controlling impedance at an edge of a circuit board includes creating a cut at an edge of a plane of the circuit board. The cut extends from the edge of the plane to a point at a depth into the plane. The method can further include creating a cut pattern in the edge of the plane by repeating the cut along the edge of the plane such that an impedance of the plane at the depth is different, or lower, than an impedance of the plane at the edge of the plane. Other aspects are described.


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