The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 15, 2023

Filed:

Jul. 22, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Meng-Hsuan Hsiao, Hsinchu, TW;

Winnie Victoria Wei-Ning Chen, Hsinchu, TW;

Tung Ying Lee, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 29/10 (2006.01); H01L 29/06 (2006.01); H01L 29/165 (2006.01); H01L 27/092 (2006.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1083 (2013.01); H01L 21/823807 (2013.01); H01L 21/823821 (2013.01); H01L 27/092 (2013.01); H01L 27/0924 (2013.01); H01L 29/0673 (2013.01); H01L 29/165 (2013.01); H01L 29/66742 (2013.01); H01L 29/78684 (2013.01); H01L 29/78696 (2013.01);
Abstract

Semiconductor structures and methods for forming the same are provided. The method includes forming a well region in a substrate and forming an anti-punch through region in a top portion of the well region. The method further includes forming a barrier layer over the anti-punch through region and alternately stacking first semiconductor material layers and second semiconductor material layers over the barrier layer. The method further includes patterning the first semiconductor material layers, the second semiconductor material layers, the barrier layer, and the anti-punch through region to form a fin and removing the first semiconductor material layers and the barrier layer to expose the anti-punch through region. The method further includes forming a gate wrapping around the second semiconductor material layers.


Find Patent Forward Citations

Hsiao, Meng-Hsuan. (2023). Method for manufacturing semiconductor structure (U.S. Patent No. 11728384). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11728384

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…