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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11728344 B1

PDFFull Text
Date of Patent:
Aug. 15, 2023

Filed:

Apr. 13, 2020

Hybrid sram design with nano-structures

Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

I-Hsieh Wong, Hsinchu, TW;

Wei-Yang Lee, Taipei, TW;

Feng-Cheng Yang, Zhudong Township, TW;

Yen-Ming Chen, Chu-Pei, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;

Attorney:

Haynes and Boone, LLP

Primary Examiner:

Errol V Fernandes

Assistant Examiner:

Jeremy J Joy

Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 29/423 (2006.01); H01L 29/06 (2006.01); H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 29/786 (2006.01); H10B 10/00 (2023.01); H01L 21/02 (2006.01); H01L 21/3065 (2006.01); H01L 29/66 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0924 (2013.01); H01L 21/02532 (2013.01); H01L 21/3065 (2013.01); H01L 29/0673 (2013.01); H01L 29/1037 (2013.01); H01L 29/42392 (2013.01); H01L 29/66439 (2013.01); H01L 29/7851 (2013.01); H01L 29/78696 (2013.01); H10B 10/12 (2023.02); H01L 21/823807 (2013.01); H01L 21/823821 (2013.01); H01L 27/0922 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01);
Abstract

A semiconductor device includes a first device disposed in an NMOS region of the semiconductor device. The first device includes a first gate-all-around (GAA) device having a vertical stack of nano-structure channels. The semiconductor device also includes a second device in a PMOS region of the semiconductor device. The second device includes a FinFET that includes a fin structure having a fin width. The fin structure is separated from an adjacent fin structure by a fin pitch. A maximum channel width of the nano-structure channels is no greater than a sum of: the fin width and the fin pitch. Alternatively, the second device includes a second GAA device having a different number of nano-structure channels than the first GAA device.

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