The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 15, 2023

Filed:

Sep. 05, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chung-Yu Lu, Hsinchu, TW;

Ping-Kang Huang, Chiayi, TW;

Sao-Ling Chiu, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 23/498 (2006.01); H01L 25/10 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5386 (2013.01); H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/56 (2013.01); H01L 23/49816 (2013.01); H01L 23/5385 (2013.01); H01L 25/105 (2013.01); H01L 23/5384 (2013.01); H01L 24/16 (2013.01); H01L 2224/16235 (2013.01);
Abstract

Board substrates, three-dimensional integrated circuit structures and methods of forming the same are disclosed. A board substrate includes a core layer, a first build-up layer, a second build-up layer, a first group of bumps, a second first group of bumps and at least one first underfill blocking wall. The first build-up layer and the second build-up layer are disposed on opposite sides of the core layer. The first group of bumps is disposed over the first build-up layer. The second first group of bumps is disposed over the first build-up layer. The at least one first underfill blocking wall is disposed over the first build-up layer and between the first group of bumps and the second group of bumps.


Find Patent Forward Citations

Lu, Chung-Yu. (2023). Board substrates, three-dimensional integrated circuit structures and methods of forming the same (U.S. Patent No. 11728278). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11728278

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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