The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 15, 2023

Filed:

May. 17, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Tsan-Chun Wang, Hsinchu, TW;

Chun-Feng Nieh, Hsinchu, TW;

Chiao-Ting Tai, New Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 21/265 (2006.01); H01L 21/3115 (2006.01); H01L 27/088 (2006.01); H01L 29/51 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823431 (2013.01); H01L 21/26506 (2013.01); H01L 21/26586 (2013.01); H01L 21/31155 (2013.01); H01L 21/823412 (2013.01); H01L 21/823462 (2013.01); H01L 21/823468 (2013.01); H01L 27/0886 (2013.01); H01L 29/517 (2013.01); H01L 21/2822 (2013.01); H01L 21/28167 (2013.01); H01L 21/28238 (2013.01);
Abstract

A method for fabricating a semiconductor device includes forming a fin extending along a first direction on a semiconductor substrate and forming a sacrificial gate electrode structure extending along a second direction substantially perpendicular to the first direction over the fin. The sacrificial gate electrode structure comprises a sacrificial gate dielectric layer and a sacrificial gate electrode layer disposed over the sacrificial gate dielectric layer. Opposing gate sidewall spacers are formed extending along the second direction, on opposing sides of the sacrificial gate electrode layer. The sacrificial gate electrode layer is removed to form a gate space. Fluorine is implanted into the gate sidewall spacers after removing the gate electrode layer by performing a first fluorine implantation. The sacrificial gate dielectric layer is removed and a high-k gate dielectric layer is formed in the gate space. Fluorine is implanted into the gate sidewall spacers and the fin after forming the high-k gate dielectric layer by performing a second fluorine implantation.


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