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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11727260 B1

PDFFull Text
Date of Patent:
Aug. 15, 2023

Filed:

Sep. 24, 2021

Applications of back-end-of-line (beol) capacitors in compute-in-memory (cim) circuits

Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Abhishek Sharma, Hillsboro, OR (US);

Jack T. Kavalieros, Portland, OR (US);

Ian A. Young, Portland, OR (US);

Ram Krishnamurthy, Portland, OR (US);

Sasikanth Manipatruni, Portland, OR (US);

Uygar Avci, Portland, OR (US);

Gregory K. Chen, Portland, OR (US);

Amrita Mathuriya, Portland, OR (US);

Raghavan Kumar, Hillsboro, OR (US);

Phil Knag, Hillsboro, OR (US);

Huseyin Ekin Sumbul, Portland, OR (US);

Nazila Haratipour, Hillsboro, OR (US);

Van H. Le, Beaverton, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:

Compass IP Law PC

Primary Examiner:

Amar Movva

Int. Cl.
CPC ...
G06N 3/063 (2006.01); H01L 27/108 (2006.01); H01L 27/11502 (2017.01); G06N 3/04 (2006.01); G06F 17/16 (2006.01); H01L 27/11 (2006.01); G11C 11/54 (2006.01); G11C 7/10 (2006.01); G11C 11/419 (2006.01); G11C 11/409 (2006.01); G11C 11/22 (2006.01); G06N 3/065 (2023.01); H10B 10/00 (2023.01); H10B 12/00 (2023.01); H10B 53/00 (2023.01);
U.S. Cl.
CPC ...
G06N 3/065 (2023.01); G06F 17/16 (2013.01); G06N 3/04 (2013.01); G11C 7/1006 (2013.01); G11C 7/1039 (2013.01); G11C 11/54 (2013.01); H10B 10/18 (2023.02); H10B 12/01 (2023.02); H10B 12/033 (2023.02); H10B 12/20 (2023.02); H10B 12/50 (2023.02); H10B 53/00 (2023.02); G11C 11/221 (2013.01); G11C 11/409 (2013.01); G11C 11/419 (2013.01);
Abstract

An apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The memory array includes an embedded dynamic random access memory (eDRAM) memory array. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes a switched capacitor circuit. The switched capacitor circuit includes a back-end-of-line (BEOL) capacitor coupled to a thin film transistor within the metal/dielectric layers of the semiconductor chip. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes an accumulation circuit. The accumulation circuit includes a ferroelectric BEOL capacitor to store a value to be accumulated with other values stored by other ferroelectric BEOL capacitors.

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