The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 15, 2023

Filed:

May. 31, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Hiranmay Biswas, Hsinchu, TW;

Chung-Hsing Wang, Hsinchu, TW;

Chin-Shen Lin, Hsinchu, TW;

Kuo-Nan Yang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 30/3947 (2020.01); G06F 30/3953 (2020.01); G06F 30/394 (2020.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01); H01L 23/528 (2006.01); H01L 23/52 (2006.01);
U.S. Cl.
CPC ...
G06F 30/392 (2020.01); H01L 23/5226 (2013.01); H01L 23/5286 (2013.01); H01L 23/53271 (2013.01); G06F 30/394 (2020.01); G06F 30/3947 (2020.01); G06F 30/3953 (2020.01);
Abstract

A method (of fabricating a power grid (PG) arrangement in a semiconductor) includes: forming a first layer including conductive lines (C_1st lines) which include interspersed alpha C_1st lines and beta C_1st lines designated correspondingly for first and second reference voltages; and forming a second layer over the first layer, the second layer including segments (C_2nd segments) which include interspersed alpha C_2nd segments and beta C_2nd segments designated correspondingly for the first and second reference voltages; and, relative to the first direction, each beta C_2nd segment being substantially asymmetrically between corresponding adjacent ones of the alpha C_2nd segments.


Find Patent Forward Citations

Loading…