The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 08, 2023

Filed:

Jan. 27, 2022
Applicant:

Mosaid Technologies Inc., Ottawa, CA;

Inventors:

Shao-Ming Yu, Hsinchu County, TW;

Chang-Yun Chang, Taipei, TW;

Chih-Hao Chang, Hsin-Chu, TW;

Hsin-Chih Chen, Taipei County, TW;

Kai-Tai Chang, Kaohsiung, TW;

Ming-Feng Shieh, Tainan County, TW;

Kuei-Liang Lu, Hsinchu, TW;

Yi-Tang Lin, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 21/67 (2006.01); H01L 27/088 (2006.01);
U.S. Cl.
CPC ...
H01L 29/785 (2013.01); H01L 21/67248 (2013.01); H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 27/0886 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/7842 (2013.01); H01L 29/7848 (2013.01); H01L 21/823412 (2013.01);
Abstract

A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.


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