The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 08, 2023

Filed:

Jul. 27, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Chien-Ling Hwang, Hsinchu, TW;

Bor-Ping Jang, Chu-Bei, TW;

Hsin-Hung Liao, Taipei, TW;

Chung-Shi Liu, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/308 (2006.01); H01L 21/306 (2006.01); H01L 21/68 (2006.01); H01L 21/67 (2006.01); H01L 21/78 (2006.01); H01L 21/683 (2006.01); C23C 16/458 (2006.01); B05C 21/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/3083 (2013.01); H01L 21/3081 (2013.01); H01L 21/30604 (2013.01); H01L 21/6708 (2013.01); H01L 21/682 (2013.01); H01L 21/6835 (2013.01); H01L 21/78 (2013.01); B05C 21/005 (2013.01); C23C 16/4585 (2013.01); H01L 21/6836 (2013.01); H01L 2221/6834 (2013.01); H01L 2221/68327 (2013.01);
Abstract

A method for thinning a wafer is provided. The method includes placing a wafer on a support assembly, and the support assembly includes a plurality of pin. The method includes securing an etching mask to a backside of the wafer, and the etching mask has an extending portion which covers a peripheral portion of the wafer. The etching mask has a plurality of circular bores extended along a vertical direction, and the etching mask is secured to the support assembly by connecting the circular bores and the pins. The method also includes performing a wet etching process on the backside of the wafer to foil a thinned wafer, wherein the thinned wafer has a peripheral portion with a first thickness and a central portion having a second thickness smaller than the first thickness.


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