The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 08, 2023

Filed:

Jan. 31, 2023
Applicant:

Powerchip Semiconductor Manufacturing Corporation, Hsinchu, TW;

Inventors:

Shou-Zen Chang, Hsinchu, TW;

Ming-Han Liao, Hsinchu, TW;

Min-Cheng Chen, Hsinchu County, TW;

Hiroshi Yoshida, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/22 (2006.01); H10B 53/30 (2023.01);
U.S. Cl.
CPC ...
G11C 11/2275 (2013.01); G11C 11/2255 (2013.01); G11C 11/2257 (2013.01); G11C 11/2273 (2013.01); H10B 53/30 (2023.02);
Abstract

An oxide semiconductor-based FRAM is provided in the present invention, including a substrate, a word line on the substrate, a gate insulating layer on the word line, an oxide semiconductor layer on the gate insulating layer, a source and a drain respectively on the oxide semiconductor layer and spaced apart at a distance, wherein the source and the drain further connect respectively to a plate line and a bit line, a ferroelectric dielectric layer on the source, the drain and the oxide semiconductor layer, and a write electrode on the ferroelectric dielectric layer, wherein the write electrode, the ferroelectric dielectric layer, the oxide semiconductor layer, the gate insulating layer and the word line overlap each other in a direction vertical to the substrate.


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