Three-dimensional memory device with support structures in gate line slits and methods for forming the same

Abstract

A method for forming a 3D memory device is provided. The method includes forming a dielectric stack including interleaved initial insulating layers and initial sacrificial layers over a substrate, and forming at least one slit structure extending vertically and laterally in the dielectric stack and dividing the dielectric stack into block regions. The at least one slit structure each includes slit openings exposing the substrate and an initial support structure between adjacent slit openings. Each block region may include interleaved insulating layers and sacrificial layers, and the initial support structure may include interleaved insulating portions and sacrificial portions. Each insulating portion and sacrificial portion may be in contact with respective insulating layers and sacrificial layers of a same level from adjacent block regions. The method also includes forming channel structures extending vertically through the dielectric stack, replacing the sacrificial layers and sacrificial portions with conductor layers and conductor portions through the at least one slit structure, and forming a source structure in each slit structure. The source structure may include an insulating spacer in each slit opening and a source contact in a respective insulating spacer.