IDiyas

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11710779 B1

PDFFull Text
Date of Patent:
Jul. 25, 2023

Filed:

Apr. 05, 2021

Semiconductor device including interface layer and method of fabricating thereof

Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chung-Liang Cheng, Changhua County, TW;

I-Ming Chang, ShinChu, TW;

Hsiang-Pi Chang, New Taipei, TW;

Yu-Wei Lu, Taipei, TW;

Ziwei Fang, Hsinchu, TW;

Huang-Lin Chao, Hillsboro, OR (US);

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;

Attorney:

Haynes and Boone, LLP

Primary Examiner:

Cheung Lee

Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/10 (2006.01); H01L 21/02 (2006.01); H01L 21/8238 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66795 (2013.01); H01L 21/02236 (2013.01); H01L 21/02381 (2013.01); H01L 21/02532 (2013.01); H01L 21/823412 (2013.01); H01L 21/823431 (2013.01); H01L 21/823462 (2013.01); H01L 21/823807 (2013.01); H01L 27/0886 (2013.01); H01L 29/1033 (2013.01); H01L 29/785 (2013.01);
Abstract

An integrated circuit device is provided that includes a first fin structure and a second fin structure extending from a substrate. The first fin structure is a first composition, and includes rounded corners. The second fin structure is a second composition, different than the first composition. A first interface layer is formed directly on the first fin structure including the rounded corners and a second interface layer directly on the second fin structure. The first interface layer is an oxide of the first composition and the second interface layer is an oxide of the second composition. A gate dielectric layer is formed over the first interface layer and the second interface layer.

Find Patent Forward Citations

Loading…