The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 18, 2023

Filed:

Aug. 08, 2022
Applicants:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Tsmc China Company, Limited, Shanghai, CN;

Tsmc Nanjing Company, Limited, Nanjing, CN;

Inventors:

XiuLi Yang, Hsinchu, TW;

Ching-Wei Wu, Hsinchu, TW;

He-Zhou Wan, Hsinchu, TW;

Kuan Cheng, Hsinchu, TW;

Luping Kong, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/18 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); G11C 8/08 (2006.01); G11C 8/10 (2006.01); G11C 11/418 (2006.01); G11C 11/419 (2006.01);
U.S. Cl.
CPC ...
G11C 8/18 (2013.01); G11C 7/106 (2013.01); G11C 7/109 (2013.01); G11C 7/1063 (2013.01); G11C 7/1087 (2013.01); G11C 7/222 (2013.01); G11C 8/08 (2013.01); G11C 8/10 (2013.01); G11C 11/418 (2013.01); G11C 11/419 (2013.01);
Abstract

A circuit includes a plurality of registers, each register including SRAM cells, a read port configured to receive a read address, a write port configured to receive a write address, a selection circuit, a latch circuit, and a decoder coupled in series between the read and write ports and the plurality of registers, and a control circuit. Responsive to a clock signal and read and write enable signals, the control circuit causes the selection circuit, the latch circuit, and the decoder to select a first register of the plurality of registers in a read operation based on the read address, and select a second register of the plurality of registers in a write operation based on the write address.


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