The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 11, 2023

Filed:

Dec. 26, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Abhishek Sharma, Hillsboro, OR (US);

Hui Jae Yoo, Hillsboro, OR (US);

Van H. Le, Beaverton, OR (US);

Huseyin Ekin Sumbul, Portland, OR (US);

Phil Knag, Hillsboro, OR (US);

Gregory K. Chen, Portland, OR (US);

Ram Krishnamurthy, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); G11C 11/407 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); G11C 11/407 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01);
Abstract

An apparatus is formed. The apparatus includes a stack of semiconductor chips. The stack of semiconductor chips includes a logic chip and a memory stack, wherein, the logic chip includes at least one of a GPU and CPU. The apparatus also includes a semiconductor chip substrate. The stack of semiconductor chips are mounted on the semiconductor chip substrate. At least one other logic chip is mounted on the semiconductor chip substrate. The semiconductor chip substrate includes wiring to interconnect the stack of semiconductor chips to the at least one other logic chip.


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