The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 04, 2023

Filed:

Feb. 22, 2021
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Charles Leon Arvin, Poughkeepsie, NY (US);

Bhupender Singh, Fishkill, NY (US);

Joseph C. Sorbello, Wappingers Falls, NY (US);

Joseph Jacobi, Hopewell Junction, NY (US);

Thomas Edward Lombardi, Poughkeepsie, NY (US);

Shidong Li, Hopewell Junction, NY (US);

Mark William Kapfhammer, Poughkeepsie, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/64 (2006.01); H01L 25/16 (2023.01);
U.S. Cl.
CPC ...
H01L 25/0652 (2013.01); H01L 23/5223 (2013.01); H01L 23/5227 (2013.01); H01L 23/5286 (2013.01);
Abstract

An integrated circuit package structure is provided that includes a chip carrier substrate, at least one processor die provided on the chip carrier substrate, a plurality of lateral escape wiring lines connected to and extending away from the at least one processor die, and a plurality of chips at least partially surrounding the processor die, at least one of the chips overlapping with at least one of the lateral escape wiring lines in a plan view. An interconnect structure of the chips includes at least one vertical power feed structure that is configured and positioned not to intersect with the lateral escape wiring lines in the plan view.


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