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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11694931 B1

PDFFull Text
Date of Patent:
Jul. 04, 2023

Filed:

Feb. 22, 2021

Metal gate structure cutting process

Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

I-Wen Wu, Hsinchu, TW;

Chen-Ming Lee, Taoyuan County, TW;

Fu-Kai Yang, Hsinchu, TW;

Mei-Yun Wang, Hsin-Chu, TW;

Chang-Yun Chang, Taipei, TW;

Ching-Feng Fu, Taichung, TW;

Peng Wang, Hsinchu, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD, Hsinchu, TW;

Attorney:

Haynes and Boone, LLP

Primary Examiner:

Farun Lu

Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 21/768 (2006.01); H01L 29/417 (2006.01); H01L 29/78 (2006.01); H01L 23/522 (2006.01); H01L 27/088 (2006.01); H01L 29/66 (2006.01); H01L 23/485 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823475 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 21/76897 (2013.01); H01L 21/823431 (2013.01); H01L 23/485 (2013.01); H01L 23/5226 (2013.01); H01L 27/0886 (2013.01); H01L 29/0642 (2013.01); H01L 29/0649 (2013.01); H01L 29/41791 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 21/823481 (2013.01);
Abstract

A semiconductor device includes a substrate, first and second fins protruding from the substrate, and first and second source/drain (S/D) features over the first and second fins respectively. The semiconductor device further includes an isolation feature over the substrate and disposed between the first and second S/D features, and a dielectric layer disposed on sidewalls of the first and second S/D features and on sidewalls of the isolation feature. A top portion of the isolation feature extends above the dielectric layer.

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