The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 04, 2023
Filed:
Sep. 25, 2020
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Inventors:
Hsiu-Wen Hsueh, Taichung, TW;
Chii-Ping Chen, Hsinchu, TW;
Po-Hsiang Huang, Taipei, TW;
Ya-Ching Tseng, Hsin-Chu, TW;
Assignee:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/535 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76844 (2013.01); H01L 21/7684 (2013.01); H01L 21/76805 (2013.01); H01L 21/76834 (2013.01); H01L 21/76846 (2013.01); H01L 21/76849 (2013.01); H01L 21/76895 (2013.01); H01L 23/535 (2013.01);
Abstract
The present disclosure relates an integrated chip. The integrated chip includes a first interconnect disposed within an inter-level dielectric (ILD) structure over a substrate. A barrier layer is disposed along sidewalls of the ILD structure. The barrier layer has sidewalls defining an opening over the first interconnect. A second interconnect is disposed on the barrier layer. The second interconnect extends through the opening in the barrier layer and to the first interconnect.