The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 27, 2023

Filed:

May. 28, 2020
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;

Inventors:

Te-Hsien Hsieh, Hsinchu, TW;

Yuan-Tai Tseng, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 45/00 (2006.01); H10B 63/00 (2023.01); H10N 70/20 (2023.01); H10N 70/00 (2023.01);
U.S. Cl.
CPC ...
H10B 63/84 (2023.02); H10B 63/24 (2023.02); H10N 70/063 (2023.02); H10N 70/24 (2023.02); H10N 70/826 (2023.02); H10N 70/841 (2023.02); H10N 70/8833 (2023.02); H10N 70/8836 (2023.02);
Abstract

A memory device including a first array of rail structures that extend along a first horizontal direction, in which each of the rail structures are formed to serve as a bottom electrode, and a second array of rail structures that laterally extend along a second horizontal direction and are laterally spaced apart along the first horizontal direction. Each of the rail structures in the second array are formed to server as a top electrode. The memory device also includes a continuous dielectric memory layer located between the first array of rail structures and the second array of rail structures. The continuous dielectric memory layer providing protection from current leakage between the rail structures of the first array and the rail structures of the second array.


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