The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 27, 2023

Filed:

Dec. 16, 2020
Applicant:

Commissariat a L'energie Atomique ET Aux Energies Alternatives, Paris, FR;

Inventors:

Emmanuel Augendre, Montbonnot, FR;

Maxime Argoud, La Chapelle de la Tour, FR;

Sylvain Maitrejean, Grenoble, FR;

Pierre Morin, Albany, NY (US);

Raluca Tiron, Saint-Martin-le-Vinoux, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78696 (2013.01); H01L 27/127 (2013.01); H01L 27/1222 (2013.01); H01L 29/1033 (2013.01); H01L 29/1037 (2013.01); H01L 29/42384 (2013.01); H01L 29/4908 (2013.01); H01L 29/66545 (2013.01); H01L 29/66742 (2013.01); H01L 29/66772 (2013.01); H01L 29/78 (2013.01); H01L 29/7842 (2013.01); H01L 29/78654 (2013.01);
Abstract

A field-effect transistor including an active zone comprises a source, a channel, a drain and a control gate, which is positioned level with the channel, allowing a current to flow through the channel between the source and drain along an x-axis, the channel comprising: a first edge of separation with the source; and a second edge of separation with the drain; the channel being compressively or tensilely strained, wherein the channel includes a localized perforation or a set of localized perforations along at least the first and/or second edge of the channel so as to also create at least one shear strain in the channel. A process for fabricating the transistor is provided.


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