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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11688794 B1

PDFFull Text
Date of Patent:
Jun. 27, 2023

Filed:

Feb. 21, 2022

Method for epitaxial growth and device

Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Tzu-Hsiang Hsu, Xinfeng Township, TW;

Ting-Yeh Chen, Hsinchu, TW;

Wei-Yang Lee, Taipei, TW;

Feng-Cheng Yang, Zhudong Township, TW;

Yen-Ming Chen, Chu-Pei, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;

Attorney:

Slater Matsil, LLP

Primary Examiner:

Errol V Fernandes

Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/165 (2006.01); H01L 29/78 (2006.01); H01L 21/02 (2006.01); H01L 21/3065 (2006.01); H01L 21/764 (2006.01); H01L 21/8238 (2006.01); H10B 10/00 (2023.01);
U.S. Cl.
CPC ...
H01L 29/66636 (2013.01); H01L 21/02507 (2013.01); H01L 21/02532 (2013.01); H01L 21/3065 (2013.01); H01L 21/764 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 21/823878 (2013.01); H01L 27/0924 (2013.01); H01L 29/0653 (2013.01); H01L 29/0847 (2013.01); H01L 29/165 (2013.01); H01L 29/66545 (2013.01); H01L 29/7848 (2013.01); H10B 10/12 (2023.02); H10B 10/18 (2023.02);
Abstract

A semiconductor device includes first and second semiconductor fins extending from a substrate and a source/drain region epitaxially grown in recesses of the first and second semiconductor fins. A top surface of the source/drain region is higher than a surface level with top surfaces of the first and second semiconductor fins. The source/drain region includes a plurality of buffer layers. Respective layers of the plurality of buffer layers are embedded between respective layers of the source/drain region.

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