The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 27, 2023

Filed:

Mar. 30, 2021
Applicant:

Adeia Semiconductor Inc., San Jose, CA (US);

Inventors:

Javier A. Delacruz, San Jose, CA (US);

David Edward Fisch, Pleasanton, CA (US);

Assignee:

Adeia Semiconductor Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/76 (2006.01); H01L 29/417 (2006.01); H01L 29/08 (2006.01); H01L 29/06 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01); H01L 21/762 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 29/4175 (2013.01); H01L 21/02532 (2013.01); H01L 21/76275 (2013.01); H01L 21/76283 (2013.01); H01L 23/538 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 29/0649 (2013.01); H01L 29/0847 (2013.01); H01L 29/66568 (2013.01); H01L 24/05 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/13016 (2013.01);
Abstract

A microelectronic unit may include an epitaxial silicon layer having a source and a drain, a buried oxide layer beneath the epitaxial silicon layer, an ohmic contact extending through the buried oxide layer, a dielectric layer beneath the buried oxide layer, and a conductive element extending through the dielectric layer. The source and the drain may be doped portions of the epitaxial silicon layer. The ohmic contact may be coupled to a lower surface of one of the source or the drain. The conductive element may be coupled to a lower surface of the ohmic contact. A portion of the conductive element may be exposed at the second dielectric surface of the dielectric layer. The second dielectric surface may be directly bonded to an external component to form a microelectronic assembly.


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