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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11688728 B1

PDFFull Text
Date of Patent:
Jun. 27, 2023

Filed:

Jul. 22, 2021

Integrated circuit structure and method for reducing polymer layer delamination

Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Jing-Cheng Lin, Hsinchu, TW;

Jui-Pin Hung, Hsinchu, TW;

Hsien-Wen Liu, Hsinchu, TW;

Min-Chen Lin, Tainan, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsin-Chu, TW;

Attorney:

Slater Matsil, LLP

Primary Examiner:

Meiya Li

Int. Cl.
CPC ...
H01L 25/00 (2006.01); H01L 23/525 (2006.01); H01L 25/065 (2023.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/532 (2006.01); H01L 23/538 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H01L 25/50 (2013.01); H01L 21/56 (2013.01); H01L 23/3114 (2013.01); H01L 23/3171 (2013.01); H01L 23/3192 (2013.01); H01L 23/49811 (2013.01); H01L 23/525 (2013.01); H01L 23/5329 (2013.01); H01L 23/5389 (2013.01); H01L 24/11 (2013.01); H01L 24/19 (2013.01); H01L 24/81 (2013.01); H01L 25/065 (2013.01); H01L 21/568 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/05027 (2013.01); H01L 2224/05166 (2013.01); H01L 2224/05582 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/11013 (2013.01); H01L 2224/1134 (2013.01); H01L 2224/1148 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/131 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/96 (2013.01); H01L 2924/181 (2013.01); H01L 2924/18162 (2013.01);
Abstract

An embodiment integrated circuit structure includes a substrate, a metal pad over the substrate, a post-passivation interconnect (PPI) structure over the substrate and electronically connected to the metal pad, a first polymer layer over the PPI structure, an under bump metallurgy (UBM) extending into an opening in the first polymer layer and electronically connected to the PPI structure, and a barrier layer on a top surface of the first polymer layer adjacent to the UBM.

Find Patent Forward Citations

Lin, Jing-Cheng. (2023). Integrated circuit structure and method for reducing polymer layer delamination (U.S. Patent No. 11688728). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11688728

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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