The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 20, 2023

Filed:

Apr. 02, 2021
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Tai-Yen Peng, Hsinchu, TW;

Hui-Hsien Wei, Taoyuan, TW;

Wei-Chih Wen, Hsinchu County, TW;

Pin-Ren Dai, Hsinchu County, TW;

Chien-Min Lee, Hsinchu County, TW;

Sheng-Chih Lai, Hsinchu County, TW;

Han-Ting Tsai, Kaohsiung, TW;

Chung-Te Lin, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10N 50/01 (2023.01); H10B 61/00 (2023.01); G11C 11/16 (2006.01); H10N 50/10 (2023.01); H10N 50/80 (2023.01); H01L 43/12 (2006.01); H01L 27/22 (2006.01); H01L 43/08 (2006.01); H01L 43/02 (2006.01);
U.S. Cl.
CPC ...
H01L 43/12 (2013.01); G11C 11/161 (2013.01); H01L 27/226 (2013.01); H01L 43/02 (2013.01); H01L 43/08 (2013.01);
Abstract

A device includes a conductive feature, a dielectric layer, a bottom electrode via, and a liner layer. The dielectric layer is over the conductive feature. The bottom electrode via is in the dielectric layer and over the conductive feature. A topmost surface of the bottom electrode via is substantially flat. A liner layer cups an underside of the bottom electrode via. The liner layer has a topmost end substantially level with the topmost surface of the bottom electrode via.


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