The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 20, 2023

Filed:

Mar. 27, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Stephanie A. Bojarski, Beaverton, OR (US);

Hubert C. George, Portland, OR (US);

Sarah Atanasov, Beaverton, OR (US);

Nicole K. Thomas, Portland, OR (US);

Ravi Pillarisetty, Portland, OR (US);

Lester Lampert, Portland, OR (US);

Thomas Francis Watson, Portland, OR (US);

David J. Michalak, Portland, OR (US);

Roman Caudillo, Portland, OR (US);

Jeanette M. Roberts, North Plains, OR (US);

James S. Clarke, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/12 (2006.01); H01L 29/78 (2006.01); H01L 27/088 (2006.01); H01L 23/528 (2006.01); G06N 10/00 (2022.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/122 (2013.01); G06N 10/00 (2019.01); H01L 21/76802 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 27/0886 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01);
Abstract

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack and a plurality of linear arrays of gates above the quantum well stack to control quantum dot formation in the quantum well stack. An insulating material may be between a first linear array of gates and a second linear array of gates, the insulating material may be between individual gates in the first linear array of gates, and gate metal of the first linear array of gates may extend over the insulating material.


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