The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 20, 2023

Filed:

Jun. 27, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Jungbae Lee, Taichung, TW;

Chih Hong Wang, Taichung, TW;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/56 (2006.01); H01L 23/29 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/563 (2013.01); H01L 23/295 (2013.01); H01L 23/3157 (2013.01); H01L 24/05 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16501 (2013.01); H01L 2224/8192 (2013.01);
Abstract

Underfill materials with graded moduli for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, the underfill material between a semiconductor die and a package substrate includes a matrix material, first filler particles with a first size distribution, and second filler particles with a second size distribution different than the first size distribution. Centrifugal force may be applied to the underfill material to arrange the first and second filler particles such that the underfill material may form a first region having a first elastic modulus and a second region having a second elastic modulus different than the first elastic modulus. Once the underfill material is cured, portions of conductive pillars coupling the semiconductor die with the package substrate may be surrounded by the first region, and conductive pads of the package substrate may be surrounded by the second region.


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