The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 20, 2023

Filed:

May. 28, 2020
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Joseph F. Maniscalco, Lake Katrine, NY (US);

Oscar van der Straten, Guilderland Center, NY (US);

Koichi Motoyama, Clifton Park, NY (US);

Choonghyun Lee, Rensselaer, NY (US);

Seyoung Kim, Weschester, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/24 (2006.01); G11C 29/00 (2006.01); G11C 13/00 (2006.01); H10B 63/00 (2023.01); H10N 70/00 (2023.01);
U.S. Cl.
CPC ...
G11C 29/886 (2013.01); G11C 13/0007 (2013.01); G11C 13/0069 (2013.01); G11C 13/0097 (2013.01); H10B 63/80 (2023.02); H10N 70/066 (2023.02); H10N 70/826 (2023.02); H10N 70/841 (2023.02); G11C 2013/0078 (2013.01); G11C 2213/15 (2013.01); G11C 2213/52 (2013.01);
Abstract

Provided are embodiments for method of fabricating a dual damascene crossbar array. The method includes forming a bottom electrode layer on a substrate and forming a first memory device on the bottom electrode layer. The method also includes forming a dual damascene structure on the first memory device, wherein the dual damascene structure includes a top electrode layer and a first via, wherein the first via is formed between the first memory device and the top electrode layer. Also provided are embodiments for the dual damascene crossbar and embodiments for disabling memory devices of the dual damascene crossbar array.


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