The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 13, 2023

Filed:

Jan. 11, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Arnab Sarkar, Chandler, AZ (US);

Sujit Sharan, Chandler, AZ (US);

Dae-Woo Kim, Phoenix, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 23/544 (2006.01); H01L 21/66 (2006.01); H01L 23/58 (2006.01); H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 25/18 (2023.01);
U.S. Cl.
CPC ...
H01L 23/49827 (2013.01); H01L 22/32 (2013.01); H01L 23/544 (2013.01); H01L 23/585 (2013.01); H01L 24/10 (2013.01); H01L 25/0655 (2013.01); H01L 24/16 (2013.01); H01L 25/18 (2013.01); H01L 2223/54426 (2013.01); H01L 2223/54453 (2013.01); H01L 2224/14 (2013.01); H01L 2224/16227 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1432 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/1517 (2013.01); H01L 2924/15192 (2013.01); H01L 2924/15313 (2013.01); H01L 2924/3512 (2013.01);
Abstract

Guard ring designs enabling in-line testing of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon. A metallization structure is disposed on the insulating layer. The metallization structure incudes conductive routing disposed in a dielectric material stack. The semiconductor structure also includes a first metal guard ring disposed in the dielectric material stack and surrounding the conductive routing. The first metal guard ring includes a plurality of individual guard ring segments. The semiconductor structure also includes a second metal guard ring disposed in the dielectric material stack and surrounding the first metal guard ring. Electrical testing features are disposed in the dielectric material stack, between the first metal guard ring and the second metal guard ring.


Find Patent Forward Citations

Loading…