The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 13, 2023

Filed:

Aug. 30, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chieh Lee, Hsinchu, TW;

Yi-Ching Liu, Hsinchu, TW;

Chia-En Huang, Xinfeng Township, TW;

Chang Jen-Yuan, Hsinchu, TW;

Yih Wang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); G11C 5/02 (2006.01); H01L 23/48 (2006.01); H01L 27/24 (2006.01); H01L 43/12 (2006.01); H01L 45/00 (2006.01); H01L 27/108 (2006.01); H01L 27/22 (2006.01); H01L 43/02 (2006.01);
U.S. Cl.
CPC ...
G11C 5/06 (2013.01); G11C 5/025 (2013.01); H01L 23/481 (2013.01); H01L 27/108 (2013.01); H01L 27/222 (2013.01); H01L 27/2481 (2013.01); H01L 43/02 (2013.01); H01L 43/12 (2013.01); H01L 45/122 (2013.01); H01L 45/16 (2013.01);
Abstract

A memory device includes a first layer, wherein the first layer includes a first memory array, a first row decoder circuit, and a first column sensing circuit. The memory device includes a second layer disposed with respect to the first layer in a vertical direction. The second layer includes a first peripheral circuit operatively coupled to the first memory array, the first row decoder circuit, and the first column sensing circuit. The memory device includes a plurality of interconnect structures extending along the vertical direction. At least a first one of the plurality of interconnect structures operatively couples the second layer to the first layer.


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