The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 13, 2023

Filed:

May. 13, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Feng Wei Kuo, Hsinchu, TW;

Shuo-Mao Chen, Hsinchu, TW;

Chin-Yuan Huang, Hsinchu, TW;

Kai-Yun Lin, Hsinchu, TW;

Ho-Hsiang Chen, Hsinchu, TW;

Chewn-Pu Jou, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 30/398 (2020.01); H01L 23/544 (2006.01); H01L 25/07 (2006.01);
U.S. Cl.
CPC ...
G06F 30/398 (2020.01); H01L 23/544 (2013.01); H01L 25/07 (2013.01); H01L 2223/54426 (2013.01);
Abstract

A method of verifying an integrated circuit stack includes adding a dummy layer to a contact pad of a functional circuit, wherein a location of the dummy layer is determined based on a location of a contact pad of a connecting substrate. The method further includes converting the dummy layer location to the connecting substrate. The method further includes performing a layout versus schematic (LVS) check of the connecting substrate including the dummy layer in response to a determination that the dummy layer is aligned with the contact pad of the connecting substrate.


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