The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2023

Filed:

Sep. 08, 2021
Applicant:

Chengdu Monolithic Power Systems Co., Ltd., Chengdu, CN;

Inventors:

Yingjiang Pu, Chengdu, CN;

Hunt Hang Jiang, Saratoga, CA (US);

Xiuhong Guo, Chengdu, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/373 (2006.01); H01L 23/552 (2006.01); C25D 5/02 (2006.01); H01L 21/48 (2006.01);
U.S. Cl.
CPC ...
H01L 23/552 (2013.01); C25D 5/022 (2013.01); H01L 21/4871 (2013.01); H01L 23/3736 (2013.01);
Abstract

A panel-shaped metal wall grids array for panel level IC packaging and associated manufacturing method. Each metal wall grid in the metal wall grids array has a continuous and closed metal wall of a predetermined wall height. The metal wall grids are connected to form a monolithic panel through a plurality of metal connecting portions. When the panel-shaped metal wall grids array is used for panel level IC packaging, at least one IC chip/IC die is disposed in each metal wall grid with a top surface of each IC chip/IC die facing downwards, and a panel-shaped metal layer matching with the panel-shaped wall grids array may be further formed on the entire back side of the panel-shaped metal wall grids array so that the panel-shaped metal layer is bonded to the metal wall of each metal wall grid.


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