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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11670597 B1

PDFFull Text
Date of Patent:
Jun. 06, 2023

Filed:

Aug. 12, 2021

Method for forming package structure

Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chin-Chuan Chang, Zhudong Township, Hsinchu County, TW;

Szu-Wei Lu, Hsinchu, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;

Attorney:

McClure, Qualey & Rodack, LLP

Primary Examiner:

Peniel M Gumedzoe

Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/78 (2006.01); H01L 21/683 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
H01L 23/5386 (2013.01); H01L 21/486 (2013.01); H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 21/6835 (2013.01); H01L 21/78 (2013.01); H01L 23/3128 (2013.01); H01L 23/5383 (2013.01); H01L 23/5384 (2013.01); H01L 24/16 (2013.01); H01L 25/0655 (2013.01); H01L 25/50 (2013.01); H01L 2221/68372 (2013.01); H01L 2224/16225 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19103 (2013.01); H01L 2924/19105 (2013.01);
Abstract

A method for forming a package structure is provided. The method includes forming a first molding compound layer surrounding a first interposer. The method also includes forming a first redistribution structure over a first side of the first interposer and the first molding compound layer. The method also includes bonding a first semiconductor die and a second semiconductor die to the first redistribution structure through a plurality of first connectors. The method also includes bonding a surface-mount device (SMD) to the first redistribution structure through a second connector. The method also includes forming a second redistribution structure over a second side of the first interposer opposite the first side of the first interposer. A top surface of the surface-mount device (SMD) is lower than top surfaces of the first semiconductor die and the second semiconductor die.

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