The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 30, 2023
Filed:
Jul. 28, 2021
Applicant:
Yangtze Memory Technologies Co., Ltd., Wuhan, CN;
Inventors:
Assignee:
YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan, CN;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 43/27 (2023.01); H01L 27/11582 (2017.01); H01L 21/28 (2006.01); C23C 28/04 (2006.01); H01L 21/02 (2006.01); H01L 21/768 (2006.01); H01L 27/1157 (2017.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); C23C 28/042 (2013.01); H01L 21/0223 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 27/1157 (2013.01); H01L 29/40117 (2019.08); H01L 29/4234 (2013.01); H01L 29/42368 (2013.01);
Abstract
A three-dimensional (3D) memory device includes a substrate, an alternating conductive/dielectric stack disposed on the substrate, an epitaxial layer disposed on the substrate, a blocking layer disposed on the epitaxial layer and surrounded by the alternating conductive/dielectric stack, a trapping layer disposed on and surrounded by the blocking layer, a tunneling layer disposed on and surrounded by the trapping layer, and a semiconductor layer disposed on and in contact with the epitaxial layer and partially disposed on and surrounded by the tunneling layer.