The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 30, 2023
Filed:
May. 23, 2022
Atomera Incorporated, Los Gatos, CA (US);
Robert John Stephenson, Duxford, GB;
Richard Burton, Phoenix, AZ (US);
Dmitri Choutov, Sunnyvale, CA (US);
Nyles Wynn Cody, Tempe, AZ (US);
Daniel Connelly, San Francisco, CA (US);
Robert J. Mears, Wellesley, MA (US);
Erwin Trautmann, San Jose, CA (US);
ATOMERA INCORPORATED, Los Gatos, CA (US);
Abstract
A vertical semiconductor device may include a semiconductor substrate having at least one trench therein, and a superlattice layer extending vertically adjacent the at least one trench. The superlattice layer may comprise stacked groups of layers, with each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer. Each at least one non-semiconductor monolayer of each group of layers may be constrained within a crystal lattice of adjacent base semiconductor portions. The vertical semiconductor device may also include a doped semiconductor layer adjacent the superlattice layer, and a conductive body adjacent the doped semiconductor layer on a side thereof opposite the superlattice layer and defining a vertical semiconductor device contact.