The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 23, 2023

Filed:

Jul. 11, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Yoshiaki Fukuzumi, Yokohama, JP;

Jun Fujiki, Tokyo, JP;

Shuji Tanaka, Kanagawa, JP;

Masashi Yoshida, Yokohama, JP;

Masanobu Saito, Chiba, JP;

Yoshihiko Kamata, Yokohama, JP;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 16/26 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 11/56 (2006.01); H01L 27/11582 (2017.01); H01L 27/11519 (2017.01); H01L 27/11565 (2017.01); H01L 27/11556 (2017.01);
U.S. Cl.
CPC ...
G11C 16/26 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 11/5628 (2013.01); G11C 11/5671 (2013.01); H01L 27/11519 (2013.01); H01L 27/11556 (2013.01); H01L 27/11565 (2013.01); H01L 27/11582 (2013.01);
Abstract

Memory might include a plurality of series-connected non-volatile memory cells, a plurality of series-connected first field-effect transistors connected in series with the plurality of series-connected non-volatile memory cells, and a second field-effect transistor, wherein the channel of the second field-effect transistor is capacitively coupled to channels of the plurality of series-connected first field-effect transistors. The memory might further include a controller configured to cause the memory to selectively activate a selected non-volatile memory cell, activate each remaining non-volatile memory cell, increase a voltage level of the respective channel of each first field-effect transistor, selectively discharge the voltage level of the respective channel of each first field-effect transistor through the selected non-volatile memory cell, and determine whether the second field-effect transistor is activated in response to a remaining voltage level of the respective channel of each first field-effect transistor.


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