The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 16, 2023

Filed:

Jul. 13, 2018
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Gulbagh Singh, Hsinchu, TW;

Chen-Hao Li, Kaohsiung, TW;

Chih-Ming Lee, Tainan, TW;

Chi-Yen Lin, Tainan, TW;

Cheng-Tsu Liu, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11568 (2017.01); H01L 29/423 (2006.01); H01L 21/28 (2006.01); H01L 29/792 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11568 (2013.01); H01L 29/40117 (2019.08); H01L 29/42348 (2013.01); H01L 29/792 (2013.01);
Abstract

The present disclosure relates to a memory device that includes a substrate and source and drain regions formed in the substrate. The memory device includes a gate dielectric formed on the substrate and between the source and drain regions. The memory device also includes a gate structure formed on the gate dielectric and the gate structure has a planar top surface. The memory device further includes a multi-spacer structure that includes first, second, and third spacers. The first spacer is formed on a sidewall of the gate structure and a top surface of one of the source and drain regions. The second spacer is formed on a sidewall of the first spacer and the second spacer has a dielectric constant greater than a dielectric constant of the first spacer. The third spacer is formed on a sidewall of the second spacer and a horizontal surface of the first spacer.


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