The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 16, 2023

Filed:

May. 07, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Khang Choong Yong, Puchong, MY;

Eng Huat Goh, Ayer Itam, MY;

Min Suet Lim, Gelugor, MY;

Robert Sankman, Phoenix, AZ (US);

Telesphor Kamgaing, Chandler, AZ (US);

Wil Choon Song, Bayan Lepas, MY;

Boon Ping Koh, Seberang Jaya, MY;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 23/31 (2006.01); H01L 23/48 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
H01L 23/5381 (2013.01); H01L 23/3178 (2013.01); H01L 23/3185 (2013.01); H01L 23/481 (2013.01); H01L 25/0655 (2013.01);
Abstract

Embodiments disclose electronic packages with a die assembly and methods of forming such electronic packages. In an embodiment, a die assembly comprises a first die and a second die laterally adjacent to the first die. In an embodiment, the first die and the second die each comprise a first semiconductor layer, an insulator layer over the first semiconductor layer, and a second semiconductor layer over the insulator layer. In an embodiment, a cavity is disposed through the second semiconductor layer. In an embodiment, the die assembly further comprises a bridge substrate that electrically couples the first die to the second die, where the bridge is positioned in the cavity of the first die and the cavity of the second die.


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