The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 02, 2023
Filed:
Mar. 25, 2019
Intel Corporation, Santa Clara, CA (US);
Jack Kavalieros, Portland, OR (US);
Ian Young, Portland, OR (US);
Matthew Metz, Portland, OR (US);
Uygar Avci, Portand, OR (US);
Chia-Ching Lin, Portland, OR (US);
Owen Loh, Portland, OR (US);
Seung Hoon Sung, Portland, OR (US);
Aditya Kasukurti, Hillsboro, OR (US);
Sou-Chi Chang, Portland, OR (US);
Tanay Gosavi, Hillsboro, OR (US);
Ashish Verma Penumatcha, Hillsboro, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Techniques and mechanisms for providing electrical insulation or other protection of an integrated circuit (IC) device with a spacer structure which comprises an (anti)ferromagnetic material. In an embodiment, a transistor comprises doped source or drain regions and a channel region which are each disposed in a fin structure, wherein a gate electrode and an underlying dielectric layer of the transistor each extend over the channel region. Insulation spacers are disposed on opposite sides of the gate electrode, where at least a portion of one such insulation spacer comprises an (anti)ferroelectric material. Another portion of the insulation spacer comprises a non-(anti)ferroelectric material. In another embodiment, the two portions of the spacer are offset vertically from one another, wherein the (anti)ferroelectric portion forms a bottom of the spacer.