The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 25, 2023

Filed:

May. 10, 2021
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Fong-yuan Chang, Hsinchu, TW;

Lee-Chung Lu, Taipei, TW;

Po-Hsiang Huang, Tainan, TW;

Chun-Chen Chen, Hsinchu County, TW;

Chung-Te Lin, Tainan, TW;

Ting-Wei Chiang, New Taipei, TW;

Sheng-Hsiung Chen, Hsinchu County, TW;

Jung-Chan Yang, Taoyuan County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/00 (2006.01); H01L 27/02 (2006.01); H01L 27/118 (2006.01); G06F 30/394 (2020.01); G06F 30/392 (2020.01);
U.S. Cl.
CPC ...
H01L 27/0207 (2013.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); H01L 27/11807 (2013.01); H01L 2027/11875 (2013.01);
Abstract

The present disclosure describes an example method for routing a standard cell with multiple pins. The method can include modifying a dimension of a pin of the standard cell, where the pin is spaced at an increased distance from a boundary of the standard cell than an original position of the pin. The method also includes routing an interconnect from the pin to a via placed on a pin track located between the pin and the boundary and inserting a keep out area between the interconnect and a pin from an adjacent standard cell. The method further includes verifying that the keep out area separates the interconnect from the pin from the adjacent standard cell by at least a predetermined distance.


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